This invention relates to a bipolar transistor suitably applied to a hetero-junction bipolar transistor and a fabrication method of the same.
A conventional hetero-junction bipolar transistor (HBT) is generally configured in such a manner as seen in FIG. 12A which is a schematic plan view and FIG. 12B which is a schematic sectional view taken along line X-X of FIG. 12A. Referring to FIGS. 12A and 12B, the hetero-junction bipolar transistor shown includes a sub collector layer 101, a collector layer 102 and a base layer 103 laminated in order on a substrate 100 made of, for example, a semi-insulating semiconductor material to form a semiconductor mesa portion BM having an upper face to which the base layer 103 is exposed. Emitter layers 104 are formed limitatively on the semiconductor mesa portion BM.
In the HBT, provision of a contact portion, through which an external wiring line for a base electrode 105 which is in ohmic contact with the base layer 103 is connected to the base electrode 105, on the semiconductor mesa portion BM increases the area of the base region and increases the capacitance between the base and the collector, and consequently deteriorates high-frequency characteristics of the transistor, that is, the characteristic frequency fT, gain and so forth of the transistor.
In order to prevent this, the base electrode 105 is extended, as seen in FIGS. 12A and 12B, to the outer side farther than the semiconductor mesa portion BM to a location on an insulating layer 106 made of, for example, SiN and formed in the form of an island on the semi-insulating semiconductor substrate. Thus, the fixed extension of the base electrode 105 on the insulating layer 106 is used as a contact portion 105C for a base wiring line.
In the configuration described, the emitter layers 104 are formed, for example, on the opposite sides of the location of the base electrode 105, and an emitter electrode 107 is formed on each of the emitter layers 104. Further, collector electrodes 108 are formed on the sub collector layer 101 on the opposite outer sides of the emitter electrodes 107.
However, where the base electrode 105 is formed in such a manner as to extend to the insulating layer 106 on the semi-insulating semiconductor substrate 100 to form the contact portion 105C as described above, there is a problem that the fabrication process therefor is much complicated and also it is difficult to control the shape the base electrode 105.
Another more simplified HBT structure has been proposed and is disclosed in Japanese Patent Laid-Open No. 2001-308312 and Technical Report of IEICE, the Institute of Electronics, Information and Communication Engineers, ED99-262. The HBT structure mentioned is shown in FIG. 13. Referring to FIG. 13, an isolation groove 210 is formed in a laminated semiconductor layer formed on a semi-insulating semiconductor substrate 200 and formed from a sub collector layer 201, a collector layer 202, a base layer 203, an emitter layer 204 and so forth. The isolation groove 210 defines a semiconductor mesa portion BM having an upper face to which the base layer 203 is exposed and an isolation portion 206 formed from part of the laminated semiconductor material separated from the semiconductor mesa portion BM. Further, a base electrode 205 is formed such that it has an extension which spans the semiconductor mesa portion BM and the isolation portion 206.
In this instance, a base wiring line contact portion 205C is a fixed extension of the base electrode 205 which is fixed to the isolation portion 206.
A collector electrode 208 is disposed on the sub collector layer 201 outside the semiconductor mesa portion BM, and an emitter electrode 207 is disposed on the emitter layer 204.
In any of the HBT described hereinabove with reference to FIGS. 12A and 12B and the HBT described above with reference to FIG. 13, the base electrode 105 or 205 has an air bridge configuration wherein it is formed such that it extends to the outer side from the semiconductor mesa portion BM and is fixed at an outer end thereof to the insulating layer 106 or the isolation portion 206 of the laminated semiconductor layer while the semiconductor layer is hollowed out below an intermediate portion of the extension so as to form an air layer.
The air layer which defines the air bridge is formed by hollowing out, after the base electrode 105 or 205 is formed, the semiconductor layer below the base electrode 105 or 205 by wet etching by which side etching of the base electrode 105 or 205 occurs.
However, in this instance, it is difficult to control the etching for the hollowing out. Further, by the etching, abnormal etching proceeds with an interface between an edge portion of the electrode and the semiconductor material, and this gives rise to such problems as deterioration of transistor characteristics, degradation of the reliability and a drop of the yield upon fabrication.
Particularly in an InP type HBT, InP is used for the substrate, and where a sub collector layer and a collector layer each formed from a semiconductor layer of an InP type which exhibits lattice matching with the InP, the side etching exhibits a high crystal selectivity. Therefore, a restriction occurs with the selection of the arrangement direction of the base electrode, and this gives rise to a restriction to the arrangement design of the base electrode. Consequently, there is a problem that the fabrication method is complicated and the yield is degraded.
Further, if the metal of the base electrode contacts at the air bridge portion with an end portion of a base mesa portion, then the stress distortion of the base metal or diffusion of the metal element reaches the semiconductor layer immediately below the same, and leak current between the base and the collector appears on a side face (end face) of the base-collector junction exposed to the side face of the mesa portion. This gives rise to a problem that there is the possibility that the reliability may be deteriorated.
Further, where a plurality of InP type HBT devices having, for example, an InGaAs layer are formed on a common substrate, since InGaAs has a small band gap, isolation of the devices cannot be achieved by application of an ordinary device isolation method by ion implantation of a neutral impurity, but it cannot be avoided to adopt the mesa structure.